1. Field of the Invention
The present invention relates generally to apparatus for facilitating communication over the Integrated Services Digital Network (ISDN), and more particularly to an improved single chip microcontroller device for use in a transceiver system adapted to communicate data from a host computer through an Integrated Services Digital Network to a destination computer. A semiconductor microcontroller located within the transceiver and coupled between the host computer and an ISDN interface includes software code, a processor and memory architecture integrated within the controller for selectably using a "shadow" personality in the memory architecture to support the software code while allowing simultaneous accessing of the memory by the computer and the processor.
2. Description of the Prior Art
In the past decade, due to many technological breakthroughs, computers have gained phenomenal popularity among users ranging across a wide spectrum of industries and personal users. This popularity has contributed to technological advancements in the efficient linking together of computers, including those located in remote areas, so that information such as digital data and voice can be transferred between computers. Furthermore, the advent of digital telephone has changed both the engineering and economic aspects of data communications. Specifically, many hardware requirements are now met with reliable and low cost digital integrated circuits (ICs). The ability to link computers through a communication medium coupled with the usage of digital telephones has lead to various communications network interconnections wherein data terminal equipment (DTE) can communicate through an Integrated Services Digital Network (ISDN). A detailed description of such a system is disclosed in U.S. Pat. No. 5,541,930 entitled "Byte Aligned Communications System For Transferring Data From One Memory To Another Memory Over An ISDN," issued to Edwin E. Klingman (hereinafter referred to as the "'930 Patent").
In FIG. 1 of the drawing, a simplified block diagram of a prior art communications system 10 is shown employing an ISDN network 12 for communicating data or voice between transceivers 14 and 16 (or between the transceivers 14 or 16 and another ISDN compatible system 17) wherein each transceiver includes a computer 18, 20 and an interface circuit 22, 24, respectively. Data and/or voice signals may be exchanged between the transceivers and/or other systems through the ISDN network 12. As further disclosed in the '930 Patent, a single transceiver can be used to communicate with any ISDN-compatible system. Within each transceiver, the included computer is capable of generating and receiving data. In the receiving mode, the interface circuits 22, 24 receive ISDN frames, having data incorporated therein, from the ISDN network 12 through communication channels 30 and 32, respectively, extract the data and transfer the extracted data to the corresponding computer 18, 20. In transmitting data, each computer 18, 20 sends data bytes through a bus 26, 28 to the corresponding interface circuit 22, 24 which in turn sends the data to the ISDN.
FIG. 2 illustrates a more detailed block diagram of the interface circuits 22 and 24 (as described in the '930 Patent) as may be employed in the system of FIG. 1. As depicted, interface circuit 22 is coupled to a computer 18 through a bus line 26 and is further coupled to an ISDN network 12 through a communication channel 30.
The ISDN network 12 includes three channels, namely the channel 34 and the B2 channel 36 (collectively referred to as the B-channels 30) and the D channel 38. B-channels 30 generally carry data bytes in 48-bit ISDN frames (for further discussion of ISDN frames, refer to the '930 Patent) and the D-channel generally carries information in 4-bit frames. As suggested at 42, the computer 18 includes driver code implementing ISDN protocol for coupling the computer 18 with the interface circuit 22.
Within the prior art interface circuit various ICs are included and are described in greater detail in the '930 Patent. Briefly, the interface circuit 22 includes a microcontroller 44, which is an IC, such as the Cy123 ISDN controller manufactured by Cybernetics Microsystems of San Gregorio, Calif., for communicating with ISDN 12 through an integrated subscriber access controller (ISAC) IC 52 such as the Siemens 2085. Initial communication occurs over the D-channel 38 of the ISDN 12 to setup and terminate connections established between transceivers through the B-channels 30. The micro-controller 44 also communicates with a host processor (not shown) such as an Intel Pentium processor, included within the computer 18, in a Microsoft Windows environment. Communication with the host processor is managed through a dual-port RAM 46 (which may comprise one or more ICs residing external to the micro-controller 44) with bi-directional interrupt facilities 48 included therein. The Cy123 chip is based on the Intel 8051 controller architecture which is well known to those skilled in the art. This controller has a Harvard architecture, which separates code and data memory spaces. Within micro-controller 44 is code ROM 50 for storing program firmware (or code) which when executed by the micro-controller, allows transfer of data between the computer 18 and ISDN 12.
While the use of discrete general-purpose components such as micro-controllers like the Cy123, dual port RAMs and subscriber access controllers, allows implementation of ISDN terminal adapters as described in the 1930 Patent, the use of these general-purpose components imposes both cost constraints and functional constraints upon the design of the communications system. This is in large part due to the fixed architecture and inflexible nature of these general-purpose components. For example, code ROM 50 in FIG. 2 stores program code that is not readily alterable and if there are any problems with the code residing therein, (these problems being commonly referred to as "bugs") , the micro-controller device may need to be entirely replaced. Furthermore, since data generally resides in shared RAM 46, accesses of such data by the micro-controller 44 entail additional time due to the shared RAM 46 being resident external to the micro-controller and embodied in a separate IC. Moreover, when program code is stored in ROM, such as in the illustrated system, system functionality can not be redefined. That is, additional features added to the ISDN network may not be readily supported by the existing program code stored in the ROM.
Furthermore, the architecture of prior art interface circuits of the type illustrated in FIG. 2 typically employ a 3-chip solution at a minimum with at least two ICs (46 and 52) including RAM memory space necessary for the storage of data, and a micro-controller which itself includes ROM memory space for storing its program code. The cost of manufacturing electronic products is in large part driven by (1) the number of components resident within the electronic product and (2) the "real-estate" each component occupies. These two criterion determine the size of the product, for example, the more components employed in an electronic device, the higher the cost of manufacturing such product. Therefore, the use of multiple ICs, as well as the fact that each IC occupies substantial real estate on the card or board on which it resides (this area of real estate is oftentimes referred to as the "footprint"), increase the expense of manufacturing. On the other hand, the use of less components on a card allows for smaller designs and lower costs.
For the foregoing reasons, there is a need for an improved microcontroller that enables the design of a more cost-effective interface for connecting a host computer system to ISDN network systems while at the same time providing a means with the flexibility to accommodate feature changes relating in either the ISDN network or in various host computers. There is also a further need for an improved microcontroller which permits modifications to its internal program code to correct problems associated therewith.